作為華邦的(竹北) DRAM Design Verification Engineer ,你將負責替客戶設計符合需求的電路圖,與製程研發/CAD/產品測試/FAE等團隊合作,完成重要專案。工作內容包含: ,以下為工作內容、工作條件以及重要通知。
【工作內容】 1. Designing and developing behavioral models for both standard and customized DRAM 2. Building and maintaining verification environments (TestBench) to ensure design quality and functional correctness 3. Participating in customer specification discussions, with the responsibility to thoroughly understand the specifications in advance to support behavioral model development
工作地點:竹北辦公室(新竹縣竹北市文興路二段539號) 聘僱性質:全職
【條件要求】
學歷要求:碩士 科系要求:電機電子工程相關 │ 資訊工程相關 │ 相關經驗:不拘 語言能力:英文 中級 │ │ 管理責任:No 輪班需求:No 出差需求:無 外派需求:No 其他條件: 1. Proficient in SystemVerilog with hands-on coding experience 2. Experience with DRAM behavioral specifications is a plus 3. Familiarity with scripting languages such as Tcl, Perl, or Python is a plus