作為華邦的(竹北) DRAM PHY Macro Design Engineer ,你將負責替客戶設計符合需求的電路圖,與製程研發/CAD/產品測試/FAE等團隊合作,完成重要專案。工作內容包含: ,以下為工作內容、工作條件以及重要通知。
【工作內容】 1. RTL design and implementation 2. RTL simulation and waveform debugging 3. Synthesis and timing analysis support 4. PHY integration and verification support 5. Collaboration with architecture, verification, analog, and backend teams
1. Proficiency in Verilog or SystemVerilog 2. Understanding of digital logic and synchronous circuit design 3. RTL simulation and debugging skills 4. DDR/LPDDR PHY design experience preferred 5. CDC/RDC, synthesis, STA, or high-speed interface knowledge preferred 6. Fluent English speaking and listening skills